Method for generating multiplier coefficients for a mixer

ABSTRACT

A mixer for mixing a digital input signal with a sampled sinusoidal signal, comprising a calculating circuit for calculating multipliers (MC) of a multiplier group (MG) which exhibits a number of dividing circuits for dividing the digital input signal applied to an input of the mixer, and a number of switchable adders/subtractors, the dividing factors of the dividing circuits being Homer coefficients of the resolved multipliers (MC) of the multiplier group (MG), the adders/subtractors being controlled in dependence on a first control bit (SUB/ADD) read out of a memory; a demultiplexer for switching through a zero value or the multiplier (MC) calculated by the calculating circuit in dependence on a second control bit (zero) read out of the memory; and comprising a sign circuit for outputting the positive or negative value switched through by the demultiplexer to an output of the mixer in dependence on a third control bit (SIGN) read out of the memory.

The invention relates to a method for generating multiplier coefficientsfor a mixer and to a mixer for mixing a digital input signal with asampled sinusoidal signal.

A modulator has inputs for a carrier quantity and for a modulatingquantity and an output for the signal produced by the modulation. Ifmodulators are used for frequency conversion, they are also calledmixers or frequency converters.

FIG. 1 shows an arrangement according to the prior art. A transmitsignal generated by a transmitter is transmitted to a receiver via atransmission channel. The receiver converts the analog input signal intoa digital signal having a particular frequency f_(s). The mixer performsa frequency conversion by multiplication in the time domain, in whichthe sampled signal having the frequency f_(s) is downconverted to anintermediate frequency IF for further data processing. The frequencyconversion takes place at a particular ratio m. In the case of GSM, forexample, m=10 whereas m=8 in the case of wireless LAN.

FIG. 2 shows the circuit configuration of a conventional 1:m mixeraccording to the prior art. The sampled signal is applied to an input Iof the mixer. The received digital signal is conducted via data lines n₁to a multiplier unit which multiplies the received digital signal bymultiplication factors MF_(i) with a particular word length WL in thetime domain. The multiplied signal is supplied to a normalizing unit andoutput via an output O of the 1:m mixer.

The mixer shown in FIG. 2 contains a storage device for storing samplesaw_(i). In the memory, for example a ROM, m samples are stored. Thesamples are cyclically read out by an address generator and applied tothe multiplier unit. The samples aw_(i) are sampled values of asinusoidal signal as shown in FIG. 3. The example shown in FIG. 3 showsthe samples which are stored in a 1:10 mixer according to the prior art.In the memory of the mixer, 10 samples of the sinusoidal signal aw₀ toaw₉ are stored. In the example shown, the stored set of multipliers is:MF_(i)=(0, +MF₁, +MF₂, +MF₂, +MF₁, 0, −MF₁, −MF₂, −MF₂, −MF₁, 0).

The mixer according to the prior art, as shown in FIG. 2, is used forshifting the frequency spectrum into the baseband of the incomingoversampled received signal. Mixing is done by the input signal beingmultiplied by the sampled sinusoidal signal as shown in FIG. 3. Themixing is preferably done after the analog/digital converter as shown inFIG. 1 since the signal processing is simpler in the baseband than inthe passband.

In the example shown in FIG. 3 of a 1:10 mixer, MF₁=sine Π/5 and/or sine36° and MF₂=sine 2 Π/5=sine 72°.

Therefore, MF₁=sine 36°=0.587785252 . . . and MF₂=sine 72°=0.951056516 .. .

If the amplitude of the received signal with a sampled sinusoidal signalis quantized, doubling the word length WL of the signal or sinusoidalsignal, respectively, produces an accuracy which is greater by 6decibels, the increase in accuracy of the ADC/DAC and of the mixercoefficients is mutually proportional. In a conventional mixer as shownin FIG. 2, the word length WL is increased until the desired accuracy isachieved.

The mixer according to the prior art, shown in FIG. 2, has thedisadvantage that the necessary word length WL is relatively great.This, in turn, has the consequence that the necessary multiplier unitcircuit can only be implemented with great complexity. In addition, thestorage space for the mixer coefficients, which is necessary for thestorage unit, is relatively great.

It is, therefore, the object of the present invention to create a methodfor generating multiplier coefficients for a mixer and a correspondingmixer in which the word length of the multiplier coefficients isrelatively small and which, nevertheless, provide very high accuracy.

According to the invention, this object is achieved by a method havingthe feature specified in claim 1 and by a mixer having the featuresspecified in claim 8 and 9, respectively.

The invention creates a method for generating multiplier coefficientsfor a 1:m mixer, comprising the following steps:

-   -   recursive calculating of a multiplier set,    -   selecting a multiplier group, consisting of a number of        multipliers, from the calculated multiplier set in dependence on        a predetermined signal/noise ratio of the mixer,    -   and writing multiplier coefficients into a memory of the mixer        in accordance with the selected multiplier group.

The method according to the invention leads to multiplier coefficientsin which, by doubling the word length WL of the multiplier coefficients,an accuracy of the mixer is achieved which is higher by 12 dB.

This results in almost perfect mixing, even if the input signals have alow amplitude and/or there are adjacent channels having high amplitudes.As a result, the necessary input word length becomes less. The result isthat the area or, respectively, the current consumption of thesubsequent stages can also be reduced.

In a preferred embodiment of the method according to the invention, themixer is a 1:10 mixer, in which, during the recursive calculation, afterinitialization

of a first multiplier V₀ of the multiplier set (MS) to zero (V₀=0) and

of a second multiplier V₁ of the multiplier set (MS) to one (V₁=1),

the further multipliers of the multiplier set (MS) are calculated inaccordance with the following recursion rule:V _(i+2) =V _(i) +V _(i+1) for all i=0, 1, 2 . . . i _(max)

In a preferred embodiment, a multiplier group consisting of twomultipliers is selected from the multiplier, the run index i of whichproduces a signal/noise ratio

$({SNR}) = {20\mspace{14mu}{{\log\lbrack \frac{1 + \sqrt{5}}{2} \rbrack}^{2} \cdot ( {i + \frac{1}{2}} )}}$which is higher than the predetermined signal/noise ratio (SNR_(NOM)) ofthe mixer.

During this process, the following multiplier coefficients (MC) arepreferably written into the memory:MC=(0, V _(i) , V _(i+1) , V _(i+1) , V _(i), 0, −Vi, −V _(i+1) , −V_(i+1) , V−V _(i),)

In a second embodiment of the 1:10 mixer, a multiplier group consistingof three multipliers is selected from the multiplier set, the run indexi of which produces a signal signal/noise ratio

$({SNR}) = {20\mspace{14mu}{{\log\lbrack \frac{1 + \sqrt{5}}{2} \rbrack}^{2} \cdot ( {i + \frac{1}{2}} )}}$which is higher than the predetermined signal/noise ratio (SNR_(NOM)) ofthe mixer.

During this process, the following multiplier coefficients (MC) arepreferably written into the memory of the mixer:MC=(V _(i) , V _(i+2), 2*V ₁₊₂ , V _(i+2) , V ₁ , −V _(i) , −V ₁₊₂, −2*V₁₊₂ , −*V _(i+2) , −V ₁)

In an alternative embodiment, the mixer is a 1:8 mixer, in which, duringthe recursive calculation after initialization of a first multiplier V₀of the multiplier set to zero (V₀=0) and of a second multiplier V₁ ofthe multiplier set (MS) to one (V₁=1), the further multipliers of themultiplier set (MS) are calculated in accordance with the followingrecursion rule:V _(i+2) =V _(i) +V _(i+1)V _(i+3) =V _(i) +V _(i+2)for all even-numbered i=0, 2, 4 . . . i_(max)

During this process, a multiplier group consisting of two multipliers isselected from the multiplier set, the run index i of which produces asignal/noise ratio SNR=20 log(1+√{square root over (2)})*i, which ishigher than the predetermined signal/noise ratio (SNR_(NOM)) of themixer.

The following multiplier coefficients (MC) are preferably written intothe memory of the mixer:MC=(0, V ₁ , V _(i+1) , V _(i), 0, −Vi, −V _(i+1) , −V ₁)

In an alternative embodiment of the 1:8 mixer, a multiplier group (MG)consisting of two multipliers (V_(i), V_(i+2)) is selected from themultiplier set (MS), the run index i of which produces a signal/noiseratio SNR=20 log[1+√{square root over (2)}](i+1) which is higher thanthe predetermined signal/noise ratio (SNR_(NOM)) of the mixer.

During this process, the following multiplier coefficients (MC) arepreferably written into the memory of the mixer:MC=(V _(i) , V _(i+2) , V _(i+2) , V _(i) , −V _(i) , −V ₁₊₂ , −V _(i+2), −V _(i))

In an alternative embodiment, the mixer is a 1:12 mixer, and during therecursive calculation after initialization of a first multiplier V₀ ofthe multiplier set (MS) to one (V₀=1) and of a second multiplier V₁ ofthe multiplier set (MS) to one (V₁=1), the further multipliers of themultiplier set (MS) are calculated in accordance with the followingrecursion rule:V _(i+2) =−V _(i)+2*V _(i+1)V _(i+3) =V _(i) +V _(i+1)V _(i+4) =V _(i)+2*V _(i+1)V _(i+5) =V _(i)+3*V _(i+1)

During this process, a multiplier group consisting of two multipliers ispreferably selected from the multiplier set, the run index i of whichproduces a signal/noise ratio

${SNR} = {20{{\log\lbrack \sqrt{2 + \sqrt{3}} \rbrack} \cdot ( {i + 2} )}}$which is higher than the predetermined signal/noise ratio (SNR_(NOM)) ofthe mixer.

The following multiplier coefficients (MC) are preferably written intothe memory of the mixer:MC=(0, V _(i) , V _(i+2), 2*V _(i) , V _(i+2) , V _(i), 0, −V _(i) , −V_(i+2), −2*V _(i), −2*V _(i+2) , −V _(i))

In an alternative embodiment of the 1:12 mixer, a multiplier groupconsisting of two multipliers (V_(i+3), V_(i+2)) is selected from themultiplier set (MS), the run index i of which produces a signal/noiseratio

${SNR} = {20{{\log\lbrack \sqrt{2 + \sqrt{3}} \rbrack} \cdot ( {i + 5} )}}$which is higher than the predetermined signal/noise ratio SNR_(NOM) ofthe mixer.

During this process, the following multiplier coefficients (MC) arepreferably written into the memory of the mixer:MC=(V _(i) , V _(i+3) , V _(i+4) , V _(i+4) , V _(i+3) , Vi, −V ₁ , −V_(i+3) , −V _(i+4) , −V _(i+4) , −V _(i+3) , −V _(i))

The multipliers of the multiplier groups (MG) are preferably resolvedinto Horner coefficients. Resolving into Horner coefficients providesthe possibility of building up the multiplier with simple shift/adderstructures. This considerably reduces the circuit complexity forimplementing the mixing unit. In addition, it makes it possible toachieve a further saving in storage space in the storage unit.

The invention also creates a mixer for mixing a digital input signalwith a sampled sinusoidal signal, comprising

-   (a) a multiplier unit for multiplying the digital input signal by    multiplier coefficients (MC);-   (b) and a coefficient memory for storing multiplier    coefficients (MC) which can be applied to the multiplier unit by    means of an address generator,-   (c) and comprising a connectable coefficient generator for    generating the multiplier coefficients (MC) by recursive calculation    of a multiplier set (MS) from which a multiplier group (MG)    consisting of a number of multipliers is selected in dependence on a    predetermined signal/noise ratio (SNR_(NOM)) of the mixer and    corresponding multipliers (MC) are written into the coefficient    memory.

The invention also creates a mixer for mixing a digital input signalwith a sampled sinusoidal signal, comprising

-   (a) a calculation circuit for calculating multipliers (MC) of a    multiplier group (MG), which exhibits a number of dividing circuits    for dividing the digital input signal applied to an input of the    mixer, and a number of switchable adders/subtractors,    -   the dividing factors of the dividing circuits being Horner        coefficients of the resolved multipliers (MC) of the multiplier        group (MG),    -   the adders/subtractors being controlled in dependence on a first        control bit (SUB/ADD) read out of a memory;-   (b) a demultiplexer for switching through a zero value or the    multiplier (MC) calculated by the calculating circuit in dependence    on a second control bit (zero) read out of the memory; and    comprising-   (c) a sign circuit for outputting the positive or negative value    switched through by the demultiplexer to an output of the mixer in    dependence on a third control bit (SIGN) read out of the memory.

The dividing circuits are preferably shift registers.

In preferred embodiments of the mixer according to the invention, anaddress generator for reading out the control bits is also provided.

The memory is preferably a read-only memory.

In an alternative embodiment, the memory is programmable.

In the text which follows, preferred embodiments of the method accordingto the invention for generating multiplier coefficients and of the mixeraccording to the invention for mixing a digital input signal with asampled sinusoidal signal are described with reference to the attachedfigures for explaining features essential to the invention.

In the Figures:

FIG. 1 shows a receiver according to the prior art;

FIG. 2 shows a 1:m mixer according to the prior art;

FIG. 3 shows a sampled sinusoidal signal according to the prior art;

FIG. 4 shows a flow chart for explaining the method according to theinvention;

FIG. 5 shows a block diagram of a first embodiment of the mixeraccording to the invention;

FIG. 6 shows a block diagram of a second preferred embodiment of themixer according to the invention;

FIG. 7 shows a table of the control signals stored in the memory of themixer shown in FIG. 6;

FIG. 8 shows a diagram of the calculated multiplier coefficients in a1:10 mixer according to the invention.

FIG. 4 shows an essential step of the method according to the inventionfor generating multiplier coefficients for a 1:m mixer according to theinvention.

After a start step S₀, after an initialization step for initializingmultipliers, multipliers of a multiplier set MS are recursivelycalculated in a step S₁.

Subsequently, a multiplier group MG for a predetermined accuracy iscalculated from the calculated multiplier set MS in a step S₂. Thepredetermined accuracy is obtained from the desired signal/noise ratioSNR_(NOM) of the mixer.

In a further step S₃, the multiplier coefficients are written into thememory of the mixer in accordance with the selected multiplier group MG.The method ends in step S₄.

The method illustrated in FIG. 4 will be explained by means of anexample in the text which follows. By way of example, multipliercoefficients for a 1:10 mixer are calculated in accordance with themethod according to the invention.

In step S₁, two multipliers V₀ and V₁ are first initialized in themethod according to the invention. During this process, multiplier V₀ isinitialized to 0 and the second multiplier V₁ is initialized to 1. V₀=0;V₁=1.

After that, further multipliers of the multiplier set (MS) arerecursively calculated in accordance with the following recursion rule:V _(i+2) =V _(i) +V _(i+1) for all i=0, 1, 2 . . . i _(max)

This recursion is a recursion rule for calculating Fibonacci numbers.The resultant multipliers of the multiplier set are:0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233, 377, 610, 987, 1597 .. .

From the calculated multiplier set MS specified above, a multipliergroup MG consisting of two multipliers V_(i), V_(i+1) are selected inaccordance with a desired signal/noise ratio SNR of the mixer, the runindex i of which produces a signal/noise ratio

$({SNR}) = {{20\mspace{14mu}{{\log\lbrack \frac{1 + \sqrt{5}}{2} \rbrack}^{2} \cdot ( {i + \frac{1}{2}} )}} = {8.36\mspace{11mu}( {i + \frac{1}{2}} )}}$which is higher than the predetermined signal/noise ratio SNR_(NOM) ofthe mixer.

After that, the calculated in-phase multiplier coefficients MC arewritten into the memory of the mixer:MC=(0, Vi, V _(i+1) , V _(i+1) , V ₁, 0, −V _(i) , −V _(i+1) , −V _(i+1), −V _(i))

In an alternative embodiment of the 1:10 mixer, the multipliercoefficients offset by Π10 are calculated instead of the in-phasemultiplier coefficients.

For this purpose, three multipliers V_(i), V_(i+1), V_(i+2) are selectedfrom the multiplier set MS calculated in step S₁, the run index i ofwhich produces a signal/noise ratio

$({SNR}) = {20\mspace{14mu}{{\log\lbrack \frac{1 + \sqrt{5}}{2} \rbrack}^{2} \cdot ( {i + 1} )}}$which is higher than the predetermined signal/noise ratio (SNR_(NOM)) ofthe mixer.

After that, the following multiplier coefficients MC are written intothe memory of the mixer in step S₃:MC=(V _(i) , V _(i+2), 2*V _(i+2) , V _(i+2) , V _(i) , −V _(i) , −V_(i+2), −2*V _(i+2) , −V _(i+2) , −V _(i))

The method according to the invention can also be used for calculatingmultiplier coefficients for a 1:8 mixer.

In this process, a first multiplier V₀ is first initialized to 0 and asecond multiplier V₁ of the multiplier set is initialized to 1.

After that, the further multipliers V_(i) of the multiplier set MS arecalculated in accordance with the following recursion rule:V _(i+2) =V _(i) +V _(i+1)V _(i+3) =V _(i) +V _(i+2)

Using this recursion rule, the following multipliers of the multiplierset MS are calculated:0, 1, 1, 1, 2, 3, 5, 7, 12, 17, 29, 41, 70, 99, 169, 239, 408, 577, 985,1393, . . .

From the calculated multiplier coefficients MC of the multiplier set(MS), a multiplier group MG consisting of two multipliers V_(i), V_(i+1)is selected, the run index i of which produces a signal/noise ratioSNR=20 log(1+√{square root over (2)})*i which is higher than thepredetermined signal/noise ratio (SNR_(NOM)) of the mixer.

In step S₃, the following eight multiplier coefficients (MC) are thenwritten into the memory of the mixer:MC=(0, V _(i) , V _(i+1) , V _(i), 0, −Vi, −V _(i+1) , −V _(i))

In an alternative embodiment for calculating the multiplier coefficientsin a 1:8 mixer, two multipliers of V_(i), V_(i+1), which form amultiplier group MG, are selected from the multiplier set MS, the runindex i of which produces a signal/noise ratio SNR=20 log(1+√{squareroot over (2)})(i+1) which is higher than the predetermined signal/noiseratio (SNR_(NOM)) of the mixer.

In step S₃, the following multiplier coefficients MC are then writteninto the memory of the mixer:MC=(V _(i) , V _(i+2) , V _(i+2) , V _(i) , −V _(i) , −V _(i+2) , −V_(i+2) , −V _(i))

In a further embodiment of the calculating method according to theinvention for calculating multiplier coefficients, multipliercoefficients for a 1:12 mixer are calculated.

During this process, a first multiplier V₀ is first initialized to 1 anda second multiplier V₁ is also initialized to 1.V ₀=1V ₁=1

After that, the further multipliers of the multiplier set MS arecalculated in accordance with the following recursion rule:V _(i+2) =−V _(i)+2*V _(i+1)V _(i+3) =V _(i) +V _(i+1)V _(i+4) =V _(i)+2*V _(i+1)V _(i+5) =V _(i)+3*V _(i+1)

The multiplier coefficients calculated in accordance with this recursionrule are obtained as:1, 1, 2, 3, 4, 5, 7, 11, 15, 19, 26, 41, 56, 71, 97, 153, 209, 265, 362,571, 780, 989, 1351, . . .

In a step S₂ of the method according to the invention, a multipliergroup MG consisting of two multipliers V_(i), V_(i+2) is selected fromthe multiplier set, the run index i of which produces a signal/noiseratio

${SNR} = {20{{\log\lbrack \sqrt{2 + \sqrt{3}} \rbrack} \cdot ( {i + 2} )}}$which is higher than the predetermined signal/noise ratio (SNR_(NOM)) ofthe mixer, where i=0, 4, 8, . . .

After that, the following twelve multiplier coefficients MC are writteninto the memory of the mixer in a step S₃:MC=(0, V _(i) , V _(i+2), 2*V _(i) , V _(i+2) , V _(i), 0, −V _(i) , −V_(i+2), 2*V _(i), −2*V _(i+2) , −V _(i)) for i=0, 1, 4, 5, 8, 9 . . .

In an alternative embodiment for calculating the multiplier coefficientsof the 1:12 mixer, a selection is made from the multiplier set MS foranother multiplier group MG consisting of two multipliers V_(i+3),V_(i+4), the run index i of which produces a signal/noise ratio

${SNR} = {20{{\log\lbrack \sqrt{2 + \sqrt{3}} \rbrack} \cdot ( {i + 5} )}}$which is higher than the predetermined signal/noise ratio SNR_(NOM) ofthe mixer, where i=1, 5, 9 . . .

The following multiplier coefficients MC are then written into thememory of the mixer in a step S₃:MC=(V _(i) , V _(i+3) , V _(i+4) , V _(i+4) , V _(i+3) , V _(i) , −V_(i) , −V _(i+3) , −V _(i+4) , −V _(i+4) , −V _(i+3) , −V _(i)) for i=1,3, 5 . . .

In the examples represented above, multiplier coefficients werecalculated for a 1:10, a 1:8 and a 1:12 mixer. With the calculatedmultiplier coefficients, 1:m mixers according to the invention as shownin FIG. 5 can be implemented. The example shown in FIG. 5 is a 1:10mixer. The mixer 1 according to the invention has a signal input 2 and asignal output 3. The digital input signal converted by theanalog/digital converter passes from the input 2 of the mixer 1 vialines 4 to a first input 5 of a multiplier unit 6. The multiplier unit 6multiplies the digital input signal by stored samples which are suppliedto the multiplier unit 6 via lines 7 from a memory 8. The number oflines between a memory 8 and a multiplier unit 6 corresponds to the wordlength of the memory WL. The multiplier coefficients MM_(i) read out ofthe memory 8 are applied to a second input 9 of the multiplier unit 6via lines 7. The multiplier unit 6 multiplies the digital input valuepresent at input 5 via the sinusoidal output value or multiplier MC_(i)to form a digital value which is output to a subsequent normalizer 12via an output 10 of the multiplier unit 6 and lines 11. The normalizer12 is connected to the output 3 of the mixer 1 according to theinvention via lines 13.

The memory 8 is enabled by an address generator 15 of the mixer 1 viaaddress lines 14. The address generator 15 cyclically activates themultiplier coefficients MC_(i), stored in the memory 8 of the memoryunit, for multiplication within the multiplier unit 6.

The stored multiplier coefficients MCI can be represented as:MCI=W _(i)×2^(k), where W _(i)≦1.

The normalizing unit 12 following the multiplier unit 6 is provided fornormalizing the output value of the multiplier unit 6, the normalizer 12essentially consisting of a shift register which shifts the output valueof the multiplier unit 6 to the right by a certain number of positions.

The memory 8 of the mixer 1 is preferably a read-only memory in whichthe calculated multiplier coefficients MCI are permanently stored.

In an alternative embodiment, the memory unit 8 is a programmable memorywhich can be connected to a multiplier coefficient generator 17 viaprogramming lines 16. In the coefficient generator 17, the multipliercoefficients are calculated in accordance with the method according tothe invention and are written into the memory 8. For this purpose, thecoefficient generator 17 can be preferably supplied with the mixingratio m and the desired signal/noise ratio SNR_(NOM) for thecalculation. The coefficient generator 17 calculates, in dependence onthe mixing ratio m=8, 10, 12 applied and the desired signal/noise ratioSNR_(NOM) the necessary multiplier coefficients MM_(i) which are storedin a memory 8.

Using the method according to the invention, multiplier coefficients canbe calculated in a simple manner for a 1:8, a 1:10 and a 1:12 mixer.During this process, multiplier coefficients MM_(i) can be calculated ineach case for an in-phase set of coefficients and an out-of-phase set ofcoefficients. The phase shift between a mixer with in-phase set ofcoefficients and a mixer with out-of-phase set of coefficients is Π/8,in the case of 1:8 mixer, Π/10 in the case of a 1:10 mixer and Π/12 inthe case of a 1:12 mixer.

According to the invention, mixers having twice the period length, i.e.a 1:16 mixer, a 1:20 mixer and a 1:24 mixer can be implemented in asimple manner by storing both the in-phase set of coefficients and theout-of-phase set of coefficients in the memory 8.

In a preferred embodiment of the mixer according to the invention, gaincontrol is also performed following the multiplier unit 6.

In the 1:m mixer according to the invention according to the firstembodiment as shown in FIG. 5, the calculated multiplier coefficients MCare distinguished by the fact that they map the sampled sine wave withthe greatest possible accuracy with a predetermined word length WL.

FIG. 6 shows a particularly preferred embodiment of the mixer 1according to the invention.

In this particularly preferred embodiment, the multiplier unit 6 shownin FIG. 5 is replaced by a shift register/adder structure so that thecircuit complexity of the mixer 1 according to the invention is greatlyreduced.

For this purpose, the multipliers of the multiplier group MG, calculatedin accordance with the invention, are split into Horner coefficients.

The Horner dissection is explained by way of example in the text whichfollows.

The embodiment shown in FIG. 6 is a 1:10 mixer. In the method accordingto the invention, the multiplier set MS consisting of many multipliersis first calculated in step S₁.

After that, two multipliers are selected as multiplier group MG from thecalculated multiplier set MS in dependence on a positive signal/noiseratio SNR_(NOM) in step S₂. In the examples shown, for example,multipliersV _(i)=55 andV _(i)1=89are selected from the multiplier set MS, which supply the desiredsignal/noise ratio SNR_(NOM).

The next higher power of 2 of the larger multiplier 89 is 128.

The two multipliers 55, 89 are resolved in accordance with the Hornerscheme, as follows:55:128=− 1/128+ 1/16−⅛+½=(((−⅛+1):2−1):4+1):289:128=+ 1/128+ 1/16+⅛+½=(((+⅛+1):2+1):4+1):2

FIG. 6 shows the circuit implementation of the mixer 1 according to theinvention for a 1:10 mixer for the multiplier coefficients 55, 89.

The mixer 1 according to the invention contains a calculating circuit 18for calculating the multiplier coefficients MC1=55 and MC2=89 of themultiplier group 55, 89. The calculating circuit 18 consists of a numberof dividing circuits 19-1, 19-2, 19-3, 19-4 and interposedadders/subtractors 20-1, 20-2, 20-3.

The dividing circuits 19-i are preferably shift registers which shiftthe applied digital value to the right by a few bits. In the case of adivision by the factor 8, for example, the digital value applied isshifted to the right by 3 bits (2³=8). The switchable adders/subtractors20-i add or subtract the applied values in dependence on a sub/addcontrol signal which is applied to the calculating circuit 18 via acontrol line 21. The associated control bit is stored in a memory 22. Inthe memory 22 of the second embodiment of the mixer 1 according to theinvention, shown in FIG. 6, in contrast to the memory 8 of the firstembodiment shown in FIG. 5, it is not the multiplier coefficient MC_(i)itself which is stored but control bits for generating the multipliercoefficients.

In the example shown in FIG. 6, the adder/subtractor unit 20-1 and theadder/subtractor unit 20/2 are supplied with the first control bitsub/add, an addition being performed when the control bit is a logical 0and a subtraction being performed when the control bit is 1.

The calculating circuit 8 is followed by a demultiplexer 23 whichreceives a zero control bit from the memory 22 via a further controlline 24.

Depending on the received zero control bit, the demultiplexer 23switches through either the multiplier MC calculated by the calculatingcircuit 18 or an applied 0. If the zero control bit is zero, thedemultiplexer 23 switches through the zero value to a subsequent signcircuit 25. If the zero control bit is logically low, the multipliervalue MC calculated by the calculating circuit 18 is conversely switchedthrough to the sign circuit 25 by the demultiplexer 23. The sign circuit25 consists of an inverting element 26, an adder 27 and a demultiplexer28 which is activated by a further control bit (SIGN) via a control line29. The inverting circuit 26 inverts the value output by thedemultiplexer 23 which is then added together with a value 1. If thecontrol bit SIGN is a logical 1, the demultiplexer 28 switches theinverted value through to the output of the mixer 1. In the conversecase, the non-inverted multiplier coefficient MC_(i) output by thedemultiplexer 28 is output.

FIG. 7 shows the memory content of the memory 22 shown in FIG. 6. In thememory 22, three control bits are in each case stored for eachmultiplier coefficient MC_(i) to be calculated of the multipliercoefficient sets MS consisting of ten coefficients so that the memorysize is 10×3 bits in the example shown. The memory size of the memory 22is thus considerably less in comparison with the memory size of themixer according to the first embodiment shown in FIG. 5 and conventionalmixers.

The address generator 15 cyclically generates the memory addresses ofthe ten registers of the memory 22, in which three control bits arelocated in each case. The sub/add, zero, SIGN control bits read outactivate the calculating circuit 8, the demultiplexer 23 and the signcircuit 25 via control lines 21, 24, 29. At the output, these generatethe two multiplier coefficients 55, 89 and −55, −89, respectively, ofthe multiplier group.

FIG. 8 shows the output of the 1:10 mixer according to the invention,shown in FIG. 6, for the two multiplier coefficients 55, 89. As can beseen in FIG. 8, the multiplier coefficients 55, 89 very accuratelyduplicate a sampled sine wave.

The 1:10 mixer shown in FIG. 6 exhibits minimum circuit complexity forthe calculating circuit 18. In addition, the memory size of the memory22 can be minimized since only control bits are stored and not themultiplier coefficients MCI themselves.

In the embodiment shown in FIG. 6, the memory 22 is a ROM memory. In analternative embodiment, the memory 22 can be programmed via programminglines.

1. A method for generating multiplier coefficients for a (1:m) mixer,comprising the steps of: (a) performing recursive calculation of amultiplier set (MS); (b) selecting a multiplier group (MG) consisting ofa number of multipliers from the calculated multiplier set (MS) independence on a predetermined signal/noise ratio (SNR_(NOM)) of themixer, wherein selecting a multiplier group (MG) comprises (i) selectinga multiplier group (MG) from the multiplier set (MS) consisting of twomultipliers (V_(i) , V _(i)+1), the run index i of which produces asignal/noise ratio (SNR)=20 log [(1+√5)/2]²·(i+1/2) that is higher thanthe predetermined signal/noise ratio (SNR_(NOM)) of the mixer, or (ii)selecting a multiplier group (MG) from the multiplier set (MS)consisting of three multipliers (Vi, Vi+1, Vi+2), the run index i ofwhich produces a signal/noise ratio (SNR)=20 log [(1+√5)/2]2·(i+1) thatis higher than the predetermined signal/noise ratio SNR_(NOM)) of themixer; (c) writing the multiplier coefficients (MC) into a memory of themixer in accordance with the selected multiplier group (MG); and (d)during the step of recursive calculation, after initialization of afirst multiplier V₀ of the multiplier set (MS) to zero (V₀=0) andinitialization of a second multiplier V₁ of the multiplier set (MS) toone (V₁=1), further multipliers of the multiplier set (MS) arecalculated in accordance with the following recursion rule:V _(i+2) =V _(i) +V _(i+1) for all i=0, 1, 2 . . . i_(max),  wherein themixer comprises a 1:10 mixer.
 2. The method as recited in claim 1,wherein the step of writing the multiplier coefficients into a memory ofthe mixer comprises: writing the following multiplier coefficients (MC)into the memory of the mixer:MC=(0, V _(i) , V _(i+1) , V _(i+1) , V _(i), 0, −V _(i) , −V _(i+1) ,−V _(i+1) −V _(i)).
 3. The method as recited in claim 1, wherein thestep of writing multiplier coefficients into a memory of the mixercomprises: writing the following multiplier coefficients (MC) into thememory of the mixer:MC=(V _(i) , V _(i+2), 2*V _(i+2) , V _(i+2) , V _(i) , −V _(i) , −V_(i+2), −2*V _(i+2) , −V _(i+2) −V _(i)).
 4. The method as recited inclaim 1, wherein the step of writing multiplier coefficients into amemory of the mixer comprises: writing the following multipliercoefficients (MC) into the memory of the mixer:MC=(0, V _(i) , V _(i+1) , V _(i), 0, −V _(i) , −V _(i+1) , −V _(i)). 5.The method as recited in claim 1, further comprising the step of:resolving the multipliers of the multiplier groups (MG) into Hornercoefficients.
 6. A method for generating multiplier coefficients for a(1:m) mixer, comprising the steps of: (a) performing recursivecalculation of a multiplier set (MS); (b) selecting a multiplier group(MG) consisting of a number of multipliers from the calculatedmultiplier set (MS) in dependence on a predetermined signal/noise ratio(SNR_(NOM)) of the mixer, wherein selecting the multiplier groupcomprises selecting the multiplier group (MG) from the multiplier set(MS) consisting of two multipliers (V_(i), V_(i+1)) the run index i ofwhich produces a signal/noise ratio (i) SNR=20 log(1+√2)*i that ishigher than the predetermined signal/noise ratio (SNR_(NOM)) or (ii)SNR=20 log [1+√2](i+1) that is higher than the predeterminedsignal/noise ratio (SNR_(NOM)) of the mixer; (c) writing the multipliercoefficients (MC) into a memory of the mixer in accordance with theselected multiplier group (MG); and (d) wherein the mixer comprises a1:8 mixer, and during the step of recursive calculation, afterinitialization of a first multiplier V₀ of the multiplier set to zero(V₀=0) and initialization of a second multiplier V₁ of the multiplierset (MS) to one (V₁=1), further multipliers of the multiplier set (MS)are calculated in accordance with the following recursion rule:V _(i+2) =V _(i) +V _(i+1)V _(i+3) =V _(i) +V _(i+2)  for all even-numbered i=0, 2, 4 . . .i_(max).
 7. The method as recited in claim 6, wherein the step ofwriting multiplier coefficients into a memory of the mixer comprises:writing the following multiplier coefficients (MC) into the memory ofthe mixer:MC=(V_(i) , V _(i+2) , V _(i+2) , V _(i) , −V _(i) , −V _(i+2) , −V_(i)).
 8. A method for generating multiplier coefficients for a (1:m)mixer, comprising the steps of: (a) performing recursive calculation ofa multiplier set (MS); (b) selecting a multiplier group (MG) consistingof a number of multipliers from the calculated multiplier set (MS) independence on a predetermined signal/noise ratio (SNR_(NOM)) of themixer, wherein selecting a multiplier group (MG) comprises (i) selectinga multiplier group (MG) from the multiplier set (MS) consisting of twomultipliers (V_(i), V_(i+2)), the run index i of which produces asignal/noise ratio${SNR} = {20{{\log\lbrack \sqrt{2 + \sqrt{3}} \rbrack} \cdot ( {i + 2} )}}$ that is higher than the predetermined signal/noise ratio (SNR_(NOM)) ofthe mixer, or (ii) selecting a multiplier group (MG) from the multiplierset (MS) consisting of two multipliers (V_(i+3)V_(i+4)) the run index iof which produces a signal/noise ratio${SNR} = {20{{\log\lbrack \sqrt{2 + \sqrt{3}} \rbrack} \cdot ( {i + 5} )}}$ that is higher than the predetermined signal/noise ratio SNR_(NOM) ofthe mixer; (c) writing the multiplier coefficients (MC) into a memory ofthe mixer in accordance with the selected multiplier group (MG); and (d)wherein the mixer comprises a 1:12 mixer, and during the step ofrecursive calculation, after initialization of a first multiplier V₀ ofthe multiplier set (MS) to one (V₀=1) and initialization of a secondmultiplier V₁ of the multiplier set (MS) to one (V₁=1), furthermultipliers of the multiplier set (MS) are calculated in accordance withthe following recursion rule:V _(i+2) =V _(i)+2*V _(i+1)V _(i+3) =V _(i) +V _(i+1)V _(i+4) =V _(i)+2*V _(i+2)V _(i+5) =V _(i)+3*V _(i+1)  for all i=0, 4, 8 . . . i_(max).
 9. Themethod as recited in claim 8, wherein the step of writing multipliercoefficients into a memory of the mixer comprises: writing the followingmultiplier coefficients (MC) into the memory of the mixer:MC=(0, V _(i) , V _(i+2), 2*V _(i) , V _(i+2) , V _(i), 0, −V _(i) , −V_(i+2), −2*V _(i), −2*V _(i+2) , −V _(i)).
 10. The method as recited inclaim 8, wherein the step of writing multiplier coefficients into amemory of the mixer comprises: writing the following multipliercoefficients (MC) into the memory of the mixer:MC=(V _(i) , V _(i+3) , V _(i+4) , V _(i+4) , V _(i+3) , V _(i) , −V_(i) , −V _(i+3) , −V _(i+4) , −V _(i+4) , −V _(i+3) , −V _(i)).
 11. Amixer for mixing a digital input signal with a sampled sinusoidalsignal, comprising: (a) a multiplier unit for multiplying the digitalinput signal by multiplier coefficients (MC); (b) a coefficient memoryfor storing multiplier coefficients (MC) are applied to the multiplierunit by means of an address generator, (c) a connectable coefficientgenerator for generating the multiplier coefficients (MC) by recursivecalculation of a multiplier set (MS) from which a multiplier group (MG)consisting of a number of multipliers is selected in dependence on apredetermined signal/noise ratio SNR_(NOM) of the mixer andcorresponding multipliers (MC) are written into the coefficient memory,wherein the multiplier group (MG) comprises a multiplier group (MG) fromthe multiplier set (MS) consisting of three multipliers (Vi, Vi+1,Vi+2), the run index i of which produces a signal/noise ratio (SNR)=20log [(1+√5)/2]2·(i+1) that is higher than the predetermined signal/noiseratio (SNR_(NOM)) of the mixer; and (d) wherein the mixer comprises a1:10 mixer, and wherein the mixer is operable during a step of recursivecalculation, after initialization of a first multiplier V₀ of themultiplier set (MS) to zero (V₀=0) and initialization of a secondmultiplier V₁ of the multiplier set (MS) to one (V₁=1), to calculatefurther multipliers of the multiplier set (MS) in accordance with thefollowing recursion rule:V _(i+2) =V _(i) +V _(i+1) for all i=0, 1, 2 . . . i _(max).
 12. A mixerfor mixing a digital input signal with a sampled sinusoidal signal,comprising: (a) a calculating circuit for calculating multipliers (MC)of a multiplier group (MG), the calculating circuit having a number ofdividing circuits for dividing the digital input signal applied to aninput of the mixer, and a number of switchable adders/subtractors,wherein dividing factors of the dividing circuits are Homer coefficientsof the calculated multipliers (MC) of the multiplier group (MG), andadders/subtractors are controlled in dependence on a first control bit(SUB/ADD) read out of a memory of the mixer; (b) a demultiplexer forswitching through a zero value or the multipliers (MC) calculated by thecalculating circuit in dependence on a second control bit (zero) readout of the memory; and (c) a sign circuit for outputting the positive ornegative value switched through by the demultiplexer to an output of themixer in dependence on a third control bit (SIGN) read out of thememory.
 13. The mixer as recited in claim 12, wherein the dividingcircuits comprise shift registers.
 14. The mixer as recited in claim 12,further comprising: an address generator for reading out the controlbits from the memory.
 15. The mixer as recited in claim 14, wherein thememory comprises a read-only memory (ROM).
 16. The mixer as recited inclaim 14, wherein the memory is programmable.